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CDP1883, CDP1883C
March 1997
CMOS 7-Bit Latch and Decoder Memory Interfaces
Description
The CDP1883 is a CMOS 7-bit memory latch and decoder circuit intended for use in CDP1800-series microprocessor systems. It can serve as a direct interface between the multiplexed address bus of this system and up to four 8K x 8-bit memories to implement a 32K-byte memory system. With four 4K x 8-bit memories, a 16K-byte system can be decoded. The device is also compatible with non-multiplexed address bus microprocessors. By connecting the clock input to VDD, the latches are in the data-following mode and the decoded outputs can be used in general-purpose memory-system applications. The CDP1833 is compatible with CDP1800-series microprocessors operating at maximum clock frequency. The CDP1883 and CDP1883C are functionally identical. They differ in that the CDP1883 has a recommended operating voltage range of 4V to 10.5V and the C version has a recommended operating voltage range of 4V to 6.5V. The CDP1883 and CDP1883C are supplied in 20 lead dualin-line plastic packages (E Suffix).
Features
* Performs Memory Address Latch and Decoder Functions Multiplexed or Non-Multiplexed * Interfaces Directly with the CDP1800-Series Microprocessors * Allows Decoding for Systems Up to 32K Bytes
Ordering Information
5V 10V TEMP. RANGE -40oC to +85oC PACKAGE PDIP PKG. NO. E20.3
CDP1883CE CDP1883E
Pinout
CDP1883, CDP1883C (PDIP) TOP VIEW
CLOCK MA0 MA1 MA2 MA3 MA4 MA5 MA6 CE
1 2 3 4 5 6 7 8 9
20 VDD 19 A8 18 A9 17 A10 16 A11 15 A12 14 CS0 13 CS1 12 CS2 11 CS3
VSS 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1507.2
4-129
CDP1883, CDP1883C
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1883C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Device Dissipation Per Output Transistor TA = Full Package Temperature Range . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Storage Temperature Range (TSTG). . . . . . . . . . . .-65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: CDP1883 CDP1883C MAX 10.5 VDD MIN 4 VSS MAX 6.5 VDD UNITS V V
PARAMETER DC Operating Voltage Range Input Voltage Range
SYMBOL
MIN 4 VSS
Static Electrical Specifications
At TA = -40oC to +85oC, VDD 5%, Except as Noted: CONDITIONS CDP1883 VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 (NOTE 1) TYP 1 10 3.2 6.4 -2.3 -4.6 0 0 5 10 CDP1883C (NOTE 1) TYP 5 3.2 -2.3 0 5 -
PARAMETER Quiescent Device Current
SYMBOL IDD
VO (V) -
VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10
MIN 1.6 3.2 -1.15 -2.3 4.9 9.9 3.5 7 -
MAX 10 100 0.1 0.1 1.5 3 1 2 2 4
MIN 1.6 -1.15 4.9 3.5 -
MAX 50 0.1 1.5 1 2 -
UNITS A A mA mA mA mA V V V V V V V V A A mA mA
Output Low Drive (Sink) Current
IOL
0.4 0.5
Output High Drive (Source) Current
IOH
4.6 9.5
Output Voltage Low-Level (Note 2)
VOL
-
Output Voltage High-Level (Note 2)
VOH
-
Input Low Voltage
VIL
0.5, 4.5 0.5, 9.5
Input High Voltage
VIH
0.5, 4.5 0.5, 9.5
Input Leakage Current
IIN
Any Input
Operating Current (Note 3)
IDD1
0, 5 0, 10
0, 5 0, 10
4-130
CDP1883, CDP1883C
Static Electrical Specifications
At TA = -40oC to +85oC, VDD 5%, Except as Noted: (Continued) CONDITIONS VO (V) VIN (V) VDD = VDR VDD = 2.4V VDD (V) CDP1883 (NOTE 1) TYP 2 CDP1883C (NOTE 1) TYP 2
PARAMETER Minimum Data Retention Voltage Data Retention Current Input Capacitance Output Capacitance NOTES:
SYMBOL VDR IDR CIN COUT
MIN -
MAX 2.4
MIN -
MAX 2.4
UNITS V A pF pF
-
0.01 5 10
1 7.5 15
-
0.5 5 10
5 7.5 15
1. Typical values are for TA = +25oC. 2. IOL = IOH = A 3. Operating current measured at 200kHz for VDD = 5V and 400kHz for VDD = 10V, with outputs open circuit.
Functional Diagram
MA0
2
D C
Q
19
A8
MA1
3
D C
Q
18
A9
MA2
4
D C
Q
17
A10
MA3
5
D C
Q
16
A11
MA4
6
D C
Q
15
A12
MA5
7
D C
Q Q
14
CS0
13 MA6 8 D C Q Q 12
CS1
CS2
CLOCK
1
11
CS3
VDD = 20 CE 9 VSS = 10
4-131
CDP1883, CDP1883C Signal Descriptions/Pin Functions
CLOCK: Latch Input Control - a high on the clock input will allow data to pass through the latch to the output pin. Data is latched on the high-to-low transition of the clock input. This pin is connected to TPA in CDP1800-series systems and tied to VDD for other applications. MA0 - MA4: Address inputs to the high-byte address latches. MA5 - MA6: High byte address inputs decoded to produce chip selects CS0 - CS3. CE: CHIP ENABLE input - A low on this pin will enable the chip select decoder. A high on this pin forces CS0, CS1, CS2, and CS3 outputs to a high (false) state. A8 - A12: Latched high-byte address outputs. CS0 - CS3: One of four latched and decoded Chip Select outputs. VDD, VSS: Power and ground pins, respectively.
TRUTH TABLE INPUTS CE 0 0 0 0 0 1 CLK 1 1 1 1 0 X MA5 0 1 0 1 X X MA6 0 0 1 1 X X 1 CS0 0 1 1 1 OUTPUTS CS1 1 0 1 1 CS2 1 1 0 1 CS3 1 1 1 0 INPUTS CE X X X X = Don't Care CLK 1 1 0 MA0 - 4 1 0 X TRUTH TABLE OUTPUTS A8 - A12 1 0 Previous State
Application Information
The CDP1883 and CDP1883C can be interfaced, without external components, with CDP1800-series microprocessor systems. These microprocessors feature a multiplexed address bus and provide an address latch signal (TPA) that is used as the clock input of the CDP1883. See Figure 2 and Figure 3. This signal is used to latch 7 bits of the high-order address. The lower five high-order address inputs are latched and held to be used with the eight lower-order address inputs to access an 8K x 8-bit memory. The two upper high-order address inputs are latched and decoded for use as chip selects. The latched address and decoding functions of the CDP1883 and CDP1883C allow them to operate with 32Kbyte memory systems. In addition, smaller memory systems can be configured with 4K x 8-bit or smaller memories, or a mix of memory sizes up to 8K x 8-bit.
Previous State 1 1 1
Dynamic Electrical Specifications
TA = -40oC to +85oC, VDD 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF. See Figure 1 CDP1883 VDD (V) (NOTE 1) (NOTE 2) TYP MAX 10 8 8 8 50 25 35 25 25 25 75 40 CDP1883C (NOTE 1) (NOTE 2) TYP MAX 10 8 50 35 25 75 -
PARAMETER Minimum Setup Time, Memory Address to CLOCK Minimum Hold Time, Memory Address After CLOCK Minimum CLOCK Pulse Width tMACL
MIN -
MIN -
UNITS ns ns ns ns ns ns
5 10
tCLMA
5 10
tCLCL
5 10
PROPAGATION DELAY TIMES Chip Enable to Chip Select tCECS 5 10 CLOCK to Chip Select tCLCS 5 10 75 45 100 65 150 100 175 125 75 100 150 175 ns ns ns ns
4-132
CDP1883, CDP1883C
Dynamic Electrical Specifications
TA = -40oC to +85oC, VDD 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF. See Figure 1 (Continued) CDP1883 VDD (V) tCLA 5 10 Memory Address to Chip Select tMACS 5 10 Memory Address to Address tMAA 5 10 NOTES: 1. Typical values are for TA = 25oC. 2. Maximum limits of minimum characteristics are the values above which all devices function. (NOTE 1) (NOTE 2) TYP MAX 100 65 100 75 80 40 175 125 175 125 125 60 CDP1883C (NOTE 1) (NOTE 2) TYP MAX 100 100 80 175 175 125 -
PARAMETER CLOCK to Address
MIN -
MIN -
UNITS ns ns ns ns ns ns
CE
VALID CHIP ENABLE tCECS tCECS
CS0, CS1, CS2, CS3 (A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
MA0 - MA5 tMACL CLOCK tCLCL CS0, CS1, CS2, CS3 tCLA A8 - A12 (B) MEMORY ADDRESS SETUP AND HOLD TIME tMAA tMAA tCLCS tMACS tMACS tCLMA
FIGURE 1. CDP1883 TIMING WAVEFORMS
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-133
CDP1883, CDP1883C
ADDRESS BUS
A0 - A7 WAIT CLR TPA CDP1800 SERIES CPU TPA CDP1837C 4K x 8 ROM
A0 - A6 CLK CDP1883 LATCH/ DECODER A8 - A12
A0 - A7
CDM6264 8K x 8 RAM
CS0 CEO CE CS1 CS2 CS3 MRD MWR MRD OE WE CE
DATA BUS
FIGURE 2. MINIMUM CDP1800-SYSTEM USING THE CDP1883 INTERFACE WITH AN 8K X 8-BIT MEMORY
CDP1883 LATCH/ DECODER CS3 CLK CE CS2 CS1
CS0 MA0 - MA6 A8 - A12
WAIT CLR ADDRESS BUS
TPA
A8 - A12 CE ADDRESS BUS A0 - A7 CDM5364 8K x 8 ROM
A8 - A12 CE A0 - A7 CDM5364 8K x 8 ROM
A8 - A12 CE A0 - A7 CDM5364 8K x 8 ROM
A8 - A12 CE A0 - A7 CDM5364 8K x 8 ROM
CDP1800 SERIES CPU MRD
DATA BUS
FIGURE 3. 32K-BYTE ROM SYSTEM USING THE CDP1883
4-134

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